Memory plays an important role in all computer systems. Dynamic random access memories (DRAMs) are commonly used as main memories in computer systems. DRAMs may be configured in bit (.times.1-bit), nibble (.times.4-bits), byte (.times.8-bits), or word (.times.16-bits) data organizations, and in speeds from about 70 ns to 150 ns. The most popular DRAMs are the large 1-bit types and nibble (.times.4) types. The DRAMs used in the computer system are typically placed on interchangeable memory cards.
In accessing a typical DRAM, multiplexed addresses are used and are split into two groups. One group designates the address of the row, while the other is used to address the column. The two groups are multiplexed onto the pins of the DRAM, first the row address signaled by a row address strobe (RAS), then the column address signaled by a column address strobe (CAS). The data is written or read to the DRAM according to a write enable (WE) signal (that follows the assertion of the CAS). There are several ways to generate the proper sequence of multiplexed addresses, RAS, CAS, and WE signals that are needed to utilize a DRAM.
Some high integration central processing unit (CPU) based systems incorporate multi-bank DRAMs. To control access to the multi-bank DRAMs, a DRAM memory controller is utilized. The DRAM memory controller generates the individual CAS signals and WE signals for each of the DRAM banks. Recently, newer DRAM configurations have become available which permit access according to a differing interface of signals. Some of these newer DRAM memory cards have multiple banks which selectively share individual CAS and WE signals. In these configurations, the CAS signals or the WE signals are logically "ORed" across bytes within the bank or across DRAM banks. In other words, some DRAM cards require one CAS and two WE signals per card or two CAS signals and one WE signal per card. Furthermore, in some single or multi-bank DRAM memory cards, CAS signals and WE signals for one bank may be used by a second DRAM bank. Thus, these newer DRAM cards share CAS signals and WE signals within a bank and across DRAM banks.
To provide an interface to the newer forms of DRAM memory cards, external logic is required. External logic provides the logical "ORing" of either the CAS or WE signals. However, the external logic introduces unwanted delays which may compromise timing margins. Furthermore, the external logic also adds to the chip count of the system. Moreover, this external logic creates a "fixed," or hard-wired, DRAM interface which precludes the use of removable and reconfigurable DRAM memory cards or a flexible DRAM upgrade.
As will be shown, the present invention programs the DRAM controller to accommodate multiple types of banks. Furthermore, the DRAM controller of the present invention accommodates multiple types of banks at the same time. The DRAM controller of the present invention provides internal logic control of the CAS and WE signals. Thus, the present invention is a DRAM controller that directly supports a wide variety of DRAM devices and also supports DRAM memory cards with no external logic.